Design Verification Engineer
Morgan Philips Group SAHsinchu職務描述Job Description :
- Senior DV role for PCIe IPs and SoC products
- Architect and build system and unit-level UVM verification environment
- Work with architects to define verification strategy and execution plans
- Review metrics and deliver task with high quality
- Analyze Functional, Code, and Test Plan Coverage
- Drive and participating in Code Reviews
- Identify, drive, and develop efficiency and IP quality improvement initiatives
- Drive root cause analysis and corrective actions for Functional bugs found in Silicon
- Drive projects from start to the finish and conduct Design verification sign-off
Minimal Qualifications :
Master’s degree in Electrical Engineering or related field5 years of industrial experience in Design VerificationProficiency in SystemVerilog and Object-Oriented ProgrammingExperience in UVM, SVA, VIP, DPIUnderstand verification best practicesExperience in PCIe protocol stackProficient scripting language in one of : Python, TCL, Shell, PerlSelf-motivated team worker 为此搜索创建职位提醒
Engineer • Hsinchu