Senior Engineer - Layout

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.

Visit our page to see what exciting opportunities and company await!

Job Description :

1. Contribute to physical layout of various memory chip circuit blocks, responsible for circuit block LVS / DRC verification.

2. Contribute to full chip level layout and verification, pattern fill and layer generation as well as tapeout process.

3. Learning the working knowledge of current CAD tools. Contribute to physical layout of various memory chip circuit blocks,

responsible for circuit block LVS / DRC verification.

Requirements / Qualifications :

1. Familiar with using Cadence Design Environment.

2. Understanding of basic CMOS design and process is a must.

Travel Time : 0% - 25%

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